From: Julien Grall <julien.grall@citrix.com>
Date: Thu, 4 Apr 2013 20:36:37 +0000 (+0100)
Subject: xen/arm: Save/Restore GICH_APR register
X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~7046
X-Git-Url: https://dgit.raspbian.org/%22http://www.example.com/cgi/%22/%22http:/www.example.com/cgi/%22?a=commitdiff_plain;h=b952c687fa17d4eab4b59f9dbb215c1e4a644fbf;p=xen.git

xen/arm: Save/Restore GICH_APR register

Linux uses GICC_CTLR.EOImodeNS set to 0, which means both priority drop and
deactivate interrupt functionality are made when something is written in
GICC_EOIR.

As the ARM manual specifies: "having an active interrupt in the List registers
with a priority that is not set in the corresponding Active Priorities
register" when GICV_CTLR.EOImode (ie GICC_CTLR.EOImodeNS in the guest context)
result in unpredicable behavior, we need to save/restore GICH_APR.

Signed-off-by: Julien Grall <julien.grall@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 49f2b203e0..3124da3c7a 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -70,6 +70,7 @@ void gic_save_state(struct vcpu *v)
         v->arch.gic_lr[i] = GICH[GICH_LR + i];
     v->arch.lr_mask = this_cpu(lr_mask);
     spin_unlock_irq(&gic.lock);
+    v->arch.gic_apr = GICH[GICH_APR];
     /* Disable until next VCPU scheduled */
     GICH[GICH_HCR] = 0;
     isb();
@@ -87,6 +88,7 @@ void gic_restore_state(struct vcpu *v)
     for ( i=0; i<nr_lrs; i++)
         GICH[GICH_LR + i] = v->arch.gic_lr[i];
     spin_unlock_irq(&gic.lock);
+    GICH[GICH_APR] = v->arch.gic_apr;
     GICH[GICH_HCR] = GICH_HCR_EN;
     isb();